Clockwork uConsole · Volume 2
The Mainboard / Carrier
Schematic theory of operation: PMIC, power tree, peripheral ICs, signal routing
Contents
1. About this Volume
This volume is the engineer-grade companion to clockwork_Mainboard_V3.14_Schematic.pdf and clockwork_Mainboard_V3.14_V5_Schematic.pdf from the uConsole repository.1 If you have the schematic open in another window, this volume is the running prose commentary: every IC role, every voltage rail traced from input to load, every quirky bit of glue logic explained.
There are two mainboard revisions in production. They are pin-compatible, share 95 % of the same circuit, and differ only in the USB power switch and the system boost converter:
| Rev | USB power switch | 5 V boost regulator | Intent |
|---|---|---|---|
| Mainboard V3.14 | SY6280 (Silergy) | SY7215 (Silergy LDO) | Stock CM4 build; ships in the original kit |
| Mainboard V3.14_V5 | TPS2553 (TI) | TPS61178 (TI boost) | Higher peak-current envelope to support CM5 properly |
Throughout this volume the unqualified phrase “the mainboard” refers to features common to both revisions. Section §17 walks through the V3.14 → V3.14_V5 deltas explicitly.
The depth target is the same as PicoCalc Volume 2: every load-bearing component on the silkscreen gets at least one paragraph; every rail gets traced from PMIC pin to load; every connector gets its pinout walked through; the quirks (PMIC latch, the dual-USB-hub topology, the keyboard’s GD32 standing in for an STM32) get the explanations they deserve.
2. Functional Block Diagram
┌──────────────────────┐
USB-C 5 V ─────────┤ │
(charge + data) │ AXP228 PMIC (U101) │ DCDC1 → SYS_3V3 (3.3 V system rail)
│ │ DCDC2 → CM_VBAT (≈4.2 V)
18650 ×2 ──────────┤ X-Powers │ DCDC3 → SYS_1V8
(3.0–4.2 V each) │ │ DCDC4 → SYS_5V boost
│ I²C: PMU-SCK/SDA │ DCDC5 → CM-related rails
│ IRQ: PMU-IRQ │ ALDO1 → AUD_3V3
│ PWRON: power btn │ ALDO2 → DISP_3V3
└──────────┬───────────┘ ALDO3 → WIFI_VDD/SYS_3V3
│ DLDO1-4, ELDO1-3 → various
▼
┌────────────────────────────┐
│ Compute-Module Connector │
│ 2× DF40C-100DS-0.4V │
│ (200 pins total) │
└──┬──────┬──────┬──────┬────┘
│ │ │ │
DSI0/1 DSI HDMI USB GPIO
↓ ↓ ↓ ↓ ↓
JD9365DA-H3 ESD5384 GL850G 40-pin
5″ 1280×720 HDMI USB hub header
(LCD + driver) protect 4-port + ID EEPROM
│
┌───────┴────────┐
│ Internal: WiFi │
│ HID kbd (GD32) │
│ External: USB-A│
└────────────────┘
┌────────────────────────────┐
│ Audio path: │
│ Codec on CM4 (BCM2711) → │
│ AS4729 analog → OCP8178 │
│ Class-D × 2 → speakers │
└────────────────────────────┘
┌────────────────────────────┐
│ Mini PCIe slot (52 pins) │
│ PCIe ×1 + USB 2.0 + SIM │
└────────────────────────────┘The mainboard is a passive carrier in the sense that the brain is on the Compute-Module side — the BCM2711 (CM4) or BCM2712 (CM5) does all the SoC-level work, and the mainboard’s role is power, peripherals, and connector breakouts. But the mainboard is not purely passive: it has the AXP228 PMIC handling the entire battery + USB-C charge path, a USB hub that fans the CM’s single USB host port out to the internal HID keyboard plus the external USB-A jack, dedicated audio amplifiers driving the speakers, ESD/level-shifter protection on HDMI, a backlight driver for the LCD, and a Mini PCIe slot that taps the CM’s PCIe lane.
3. The AXP228 PMIC (U101)
The AXP2282 is an X-Powers system PMIC originally targeted at small Android tablets and handhelds. It integrates on a single die: a Li-ion battery charger, a fuel-gauge, five DC-DC switching regulators, three ALDO general-purpose LDOs, four DLDO digital-rail LDOs, and three ELDO LDOs intended for SoC-internal blocks. It speaks to the host over a 2-wire I²C-style interface (PMU-SCK / PMU-SDA on the schematic) plus a single IRQ line (PMU-IRQ), a hardware power-button input (PWRON), and a power-OK output (PWROK).
3.1 Why this matters
Every voltage rail on the mainboard (and most rails downstream of the CM connector) is sourced from the AXP228. Understand the AXP228 and you understand the power architecture; misunderstand it (or skip it) and the famous “PMIC latch” quirk in §15 stops being a one-paragraph footnote and becomes inscrutable.
3.2 The five DC-DCs
The DCDC outputs are the workhorses — high efficiency switchers running in the 1.5 MHz range, each providing several hundred milliamps to a multi-amp load class. From the schematic:
| Output | Schematic net | Typical voltage | Load |
|---|---|---|---|
| DCDC1 | SYS_3V3 | 3.3 V | Mainboard 3.3 V rail; feeds GL850G hub, peripheral logic |
| DCDC2 | CM_VBAT | ≈ 4.2 V | CM connector “battery” rail (CM uses this for its on-module SMPS) |
| DCDC3 | SYS_1V8 | 1.8 V | Level-shifter low side, ID EEPROM, signal-routing logic |
| DCDC4 | SYS_5V | 5 V | The shared 5V rail; powers USB hub, USB-A Vbus, audio |
| DCDC5 | DC5LDO / aux | Programmable | Reserved / auxiliary in the uConsole load profile |
DCDC4 is unusual — it’s a boost function in the V3.14_V5 rev when run from a single-cell 18650 (which sits at 3.0–4.2 V; the AXP228’s DCDC4 alone can’t push to 5 V from that input). The mainboard backs DCDC4 with the SY7215 (V3.14) or TPS61178 (V3.14_V5) boost converter for the times when DCDC4 is being used as a 5 V supply rail rather than a 3 V or lower programmable rail. The schematic’s IPSOUT1/IPSOUT2 and SYS_5V nets are the input and output sides of that boost.
3.3 ALDO / DLDO / ELDO
These are linear LDOs with low quiescent current, intended for analog and signal-quality-sensitive loads where the PWM ripple of a switcher would be unwelcome.
| Output | Net | Typical voltage | Load |
|---|---|---|---|
| ALDO1 | AUD_3V3 | 3.3 V | Audio analog rail; powers the AS4729 / OCP8178 circuit |
| ALDO2 | DISP_3V3 | 3.3 V | LCD logic rail; supplies the JD9365DA-H3 driver IC |
| ALDO3 | WIFI_VDD / SYS_3V3 (jumper-selected) | 3.3 V | Internal WiFi/BT subsystem (CM4) when present |
| DLDO1-4 | ELDO1-3 | 1.2–3.3 V | Programmable per-rail; reserved for SoC-side power supplies that the CM module itself routes |
| ELDO1-3 | Various | 1.8 / 3.0 V | Programmable; auxiliary peripheral rails |
The mainboard schematic ties many of these LDO outputs to 10 µF bulk + 100 nF decoupling. That is exactly per the AXP228 datasheet and not a uConsole-specific design choice.
3.4 Charger and fuel-gauge
The AXP228 contains a Li-ion linear charger sized to charge two 18650 cells in series-or-parallel-as-configured. The schematic shows the cells’ positive terminals routed to VBAT via 0R / 0R-replaceable footprints — the cells run in parallel in the uConsole topology (not series), so total pack capacity is doubled (≈ 6.0 Ah for two 3000 mAh MJ1 cells) and total pack voltage stays at single-cell levels (3.0–4.2 V).
The fuel-gauge has the standard X-Powers algorithm — Coulomb counting from a sense resistor (the schematic’s 0R01 1% shunts in series with the battery negative path), with a periodic open-circuit-voltage recalibration. Linux exposes the fuel-gauge state via /sys/class/power_supply/uconsole_battery/ once the Clockwork patches are loaded (Vol 6).
The charger sources up to 2.5 A from IPSOUT (the input-power-source-out node, fed from USB-C); the schematic’s IPSOUT1/IPSOUT2 are the USB-C and battery presents to the AXP228. Charge current is programmable; the default is conservative (1.5 A typical) which is appropriate for an unregulated “5 V 2 A” wall wart per the assembly guidelines.3
3.5 The PWRON / PWROK / IRQ trio
PWRON is wired to the physical power button on the back of the case. The AXP228 implements the canonical short-press / long-press / very-long-press sequence:
- Short press from off: power on (sequence: enable DCDC1-4, then ALDO1-3, then
PWROKasserted; CM4 seesRUNgo high and starts boot). - Short press from on: send IRQ to the CM (graceful shutdown trigger; user-space dispatches
systemd-logind suspend / power-off). - Long press (~6 s) from on: hard power-off (force cut of all rails). This is a brutal shutdown — bypasses Linux. Use sparingly.
- Very-long press (~10 s+): factory PMIC reset; behaves as if cells were physically removed.
PWROK is the AXP228’s notification to the rest of the board that power rails are stable. It’s tied to RUN on the CM connector through 0R / 0R-NC footprints — so power-good gates CM boot.
PMU-IRQ is bidirectional: AXP228 raises it on charger insertion, charger removal, low-battery, over-temperature, button press, and reset events. The kernel’s axp20x driver consumes those events.
4. Power Tree (V3.14)
The full tree, traced from external sources to load:
USB-C (5 V, 2 A nominal) ──┐
├──► AXP228 IPSOUT (charger input)
2× 18650 in parallel ──────┘ │
▼
┌───── DCDC1 ──► SYS_3V3 ──┬─► GL850G U501 (Vcc)
│ ├─► CM_3V3 (CM rail input)
│ ├─► Pull-ups, signal-routing logic
│ └─► Mini PCIe slot 3V3 reference
│
├───── DCDC2 ──► CM_VBAT ──► CM4/CM5 module battery input
│
├───── DCDC3 ──► SYS_1V8 ──┬─► Level-shifter low side
│ ├─► ID EEPROM
│ └─► CM_1V8
│
├───── DCDC4 + SY7215/TPS61178 boost ──► SYS_5V ──┬─► U501 (GL850G core)
│ ├─► U502 (USB-A switch in)
│ ├─► OCP8178 audio amps
│ └─► Mini PCIe Vcc-aux
│
├───── ALDO1 ──► AUD_3V3 ──► AS4729 / audio analog
│
├───── ALDO2 ──► DISP_3V3 ──► JD9365DA-H3 logic
│
├───── ALDO3 (jumper) ──► WIFI_VDD / SYS_3V3 alt
│
├───── DLDO1-4 ──► CM-side aux rails
│
└───── ELDO1-3 ──► reservedEvery output rail has a 10 µF X5R bulk capacitor sitting on it close to the pin, plus a 100 nF X7R decoupling cap distributed across the load. That’s per AXP228 datasheet and not reverse-engineered prudence.
The IPS net (input-power-select) appears on most schematic capacitor-bank diagrams — this is the AXP228’s internal “either USB or battery” merge point, not a separate rail. Any net labelled IPS is connected to IPSOUT electrically.
5. The Compute-Module Connector
The mainboard uses two DF40C-100DS-0.4V Hirose 0.4 mm-pitch board-to-board sockets4 (call them J1, J2 in the silkscreen — 100 pins each, 200 total). This is the canonical CM4 mezzanine pinout.5 The CM4 / CM5 module presents the matching plug; the mainboard’s two sockets receive it.
5.1 Pin groups (signal class)
The 200-pin connector clusters by function. A summary:
| Pin range | Function class | Mainboard handling |
|---|---|---|
| 1–10 | SD card | Routed to internal SD slot (CM4 Lite reads SD) |
| 11–24 | GPIO group A (audio) | Routed to CM connector breakout |
| 25–46 | GPIO group B (general) | Routed to 40-pin GPIO header on the back |
| 47–66 | DSI0 (display) | Routed to JD9365DA-H3 LCD driver |
| 67–86 | HDMI0 | Routed to ESD5384 protection then micro-HDMI jack |
| 87–106 | DSI1 (display alt) | Reserved on uConsole (DSI0 carries the LCD) |
| 107–134 | HDMI1 | Reserved (only one micro-HDMI exposed) |
| 135–158 | CAM0/CAM1 | Reserved (no camera connector on uConsole) |
| 159–166 | USB host | Routed to GL850G hub |
| 167–186 | DSI1_D2/D3 + reserved | Mostly reserved |
| 187–200 | Power / ground | CM_VBAT, CM_3V3, CM_1V8, RUN, GND |
The full pin-by-pin map is in the schematic; this section’s summary is what most readers want first.
5.2 Critical signals not to break
A small set of signals must work for the mainboard to be useful at all. If any of these go open, you get a no-boot or partial-boot failure:
RUN— drive low, CM stays in reset; drive high (or float — internal pull-up), CM boots. Tied to AXP228PWROKthroughR120 0R / R121 0R-NC(a board-mode jumper). WhenR120is populated andR121is not,PWROKgatesRUN. WhenR121is populated andR120is not,RUNis fixed high (PMIC bypass for debug). Stock uConsole ships withR120 0R, R121 NC— i.e., the PMIC is in charge.GLOBAL_EN— global enable signal for the CM. On the uConsole, tied toRUNthrough 0R.nEXTRST— external reset; tied to a 100 nF cap to ground for power-on reset timing. Pull low to force a CM reset.nRPIBOOT— pull low at boot for the CM’s USB-MSD recovery mode (see Vol 4 §4.4). On the mainboard, exposed via a small button or solder jumper in the V5 rev; on V3.14 it’s a solder pad on the back of the board.SD_PWR_ON— drive high to power the SD card slot. On uConsole, tied to a constant 3V3 (always-on) when CM4 Lite is in use, since SD is the primary boot device.PI_LED_nPWR— drives the small green LED next to the power button. Inverted (low = lit).
6. Display Path — DSI0 to JD9365DA-H3
The 5″ 1280×720 IPS LCD is driven by the JD9365DA-H3 display driver IC.6 DSI0 from the CM connector enters the panel module; the JD9365 handles MIPI-DSI deserialisation, gamma, panel timings, and the high-voltage row/column drive for the LCD itself. The mainboard’s role here is largely passive: route the DSI lanes, provide the 3.3 V logic rail (DISP_3V3 via ALDO2), and supply the backlight.
6.1 DSI lane routing
DSI0 is a 4-lane MIPI-DSI bus plus a clock pair, all routed differentially from CM connector pins 47–60 to the LCD module via a 30-pin FPC connector on the front edge of the mainboard. The mainboard treats each pair as a controlled-impedance 100 Ω differential trace; at MIPI-DSI HS mode (~600 Mbps per lane on CM4, up to 2.5 Gbps per lane on CM5) the trace length matching is inside ±10 mil (datasheet requirement is ±50 mil so there’s plenty of margin).
The schematic shows a DSI0_CN/DSI0_CP differential pair plus four data pairs (DSI0_D0-D3 × N/P). DSI1 is the secondary lane group (pins 87–106) and is unused on the uConsole — those pins fan out to test pads that aren’t populated in production.
6.2 Backlight
The LCD’s backlight is a multi-LED string driven from LEDA (anode) to LEDK (cathode); typical drop is 12–16 V and the string runs at 20–80 mA (programmable PWM duty). The backlight driver is U302 — implementing a small inductive boost from SYS_5V to the backlight string voltage, with PWM dimming controlled from a CM GPIO. The schematic shows the 10 µH / 0.5 A inductor (L302) and the typical Schottky-diode + Cout / Rsense topology.
Linux exposes the brightness at /sys/class/backlight/uconsole_backlight/brightness (range 0–255). Vol 12 §11.2 has the recipes.
6.3 The display 3.3 V rail and quirks
DISP_3V3 from ALDO2 drives the JD9365’s VCC input. This rail has two distinguishing characteristics on the schematic:
- It is independently switchable by the AXP228 via I²C — so a Linux
dpms offcan drop the LCD’s main rail to true 0 V (rather than just blanking the data lines). - It is gated on
DISP_3V3rising before DSI traffic begins — the kernel’s display pipeline driver waits ~20 ms after enabling ALDO2 before issuing DSI INIT commands. If you skip this, the JD9365 misses the init sequence and you get a black screen with backlight on.
This second behaviour is one of the things the Clockwork kernel patches handle (Vol 6 §6.5).
7. Audio Path
The mainboard implements a stereo speaker chain plus a headphone jack with auto-detect. The signal flow is:
CM connector PCM_OUT (audio) ──► CM4-internal codec (BCM2711 has analog out via PWM)
│
▼
┌───────────┐
│ AS4729 │ Analog input switch / muxing
└─────┬─────┘
│
┌────────┴────────┐
▼ ▼
OCP8178 L OCP8178 R (Class-D mono speaker amps)
(U401-U402) (U403-U404)
│ │
▼ ▼
LEFT speaker RIGHT speaker
(J401) (J402)
┌───────────┐
│ AS4729 │
│ Switch │
└─────┬─────┘
│
▼
Headphone jack
(J403; uses HPOL/HPOR)7.1 The CM4 doesn’t have a real codec
On a Pi 4 / CM4, “audio out” is implemented as PWM on a GPIO — the BCM2711 doesn’t have an integrated I²S codec for line-out. The PWM generates a 1.5 MHz carrier whose duty-cycle is the audio sample; an external low-pass filter (the RC chain visible as R413 47K / C411 15nF and siblings on the schematic) integrates that PWM into an analog audio signal. This is the same trick the Pi has used since 2012; it’s good enough for casual listening and cheap, but it’s why the CM4 audio out has more THD+N than a proper I²S codec would.
The CM5 has a full I²S codec on-chip; the same RC filters are present on the mainboard but bypassed (the codec drives the analog stages directly).
7.2 OCP8178 speaker amplifiers
The OCP81787 is a Class-D mono speaker amplifier with a typical 2 W output into 4 Ω at 5 V. On the uConsole mainboard it appears four times — once per output channel for each speaker (two devices per channel, in a paralleled bridge-tied-load topology that doubles peak current and roughly doubles peak power). The schematic shows R415 / R418 (gain-set), C2 (input coupling), EN (enable, pulled to a CM GPIO so audio can be muted by software), and PA_EN (separate amp enable used during boot mute).
The amps’ supply is SYS_5V (DCDC4 + boost). Their disable line is asserted briefly during PMIC ramp-up to suppress the audible “thump” when speakers go hot.
7.3 AS4729 analog routing
The AS4729 is an analog-switch / muxing IC that selects between the speaker-amp path and the headphone-jack path based on the headphone-detect signal (HPOL, HPOR on the CM connector). When a headphone plug is inserted, the switch routes audio to the jack and disables the speaker amps via a logic-level signal. This is in hardware — the CM doesn’t need to know.
7.4 The microphone path
Pin MICBIAS is a 2.4 V reference voltage routed to the headphone jack’s microphone pad (TRRS-style 4-conductor jack). The CM4’s MICP/MICN analog differential pair receives the mic signal, with a small RC filter on the schematic. The CM4’s internal ADC (or, in CM5, the I²S codec) handles digitization.
8. Keyboard Subsystem
The 74-key backlit keyboard is a separate PCB mounted in the front panel of the uConsole. It is electrically connected to the mainboard via a single ribbon cable that carries USB D+/D−, 5 V, GND, and the keyboard backlight PWM line.
The keyboard PCB is its own small system. Its schematic (keyboard_220816.pdf) shows:
- U1: GD32F103Rx8 — a GigaDevice ARM Cortex-M3 microcontroller in 64-pin LQFP, pin-compatible drop-in replacement for the STM32F103R8T6.
- X1: 8 MHz HSE crystal (with
C9 20pF,R1 1MΩ,C10 20pFper the canonical STM32 HSE topology). - X2: 32.768 kHz LSE crystal (RTC;
C11 10pF,C12 10pF). Yes, the keyboard has its own RTC reference — used for keypress timing and Power-LED PWM. - U2-U7: Five “AN48841” small protection / buffer ICs on the row/column lines (per silk; specific manufacturer not stamped — likely a 5-pin tactile-switch debounce / reset device; schematic does not provide a definitive part identifier).
- LM1117S-3.39: 3.3 V LDO regulator on the keyboard board. Input 5 V from the ribbon cable, output 3.3 V to the GD32 and supporting logic.
- R10 1.5 kΩ: Pull-up on USB D+ — standard USB full-speed enumeration pull-up. The keyboard PCB exposes itself to the host as a USB HID device.
- R8 / R9 22 Ω: Series termination on USB D+/D− — standard for cable-driven USB.
8.1 What the GD32 actually does
The GD32 implements:
- A USB HID device (full-speed, 12 Mb/s) that the CM enumerates as
idVendor=0x1209 idProduct=...(Clockwork-allocated VID/PID). Standard HID keyboard report descriptor. - Key matrix scanning: 16 rows × 8 cols × 1 ms per scan = ~125 Hz scan rate, plenty for fast typing.
- Debounce: 20 ms per-key minimum.
- Layer logic: the
Fnmodifier produces alternate codes for the keys it overlays (F1–F12, brightness, volume, etc. — see Vol 12 §5). - Backlight PWM: the keyboard’s white-LED backlight is on a 1 kHz PWM driven by GD32 pin PA9 (configured as a TIM2 channel). Duty cycle is set via a custom HID feature report from the CM.
- Game-button reading: A/B/X/Y are wired into the same matrix as ordinary keys — they appear as keysyms
Return,Escape,space,Tabby default (remappable in software). - D-pad reading: also part of the matrix; produces standard arrow-key reports.
8.2 Why this matters
You can re-flash the GD32. The bootloader is the standard ST DFU bootloader, accessible by holding the BOOT0 line high at reset (test pad on the keyboard PCB). The custom firmware Clockwork ships is open-source and lives in the uConsole repo at Code/keyboard/ — modifying it lets you remap the layer behaviour, change the matrix mapping, or add macros without involving the CM’s user-space.
9. USB Topology
The mainboard takes the CM’s single USB host port and fans it out via a hub. This is essential because the CM4 / CM5 only expose one USB port through the connector (the other USB pairs on the silicon are either in-use for on-module radio or routed to the SD slot’s eUFS path).
9.1 The GL850G hub
U501: GL850G10 is a Genesys Logic 4-port USB 2.0 hub controller, single-TT (Transaction Translator). On the uConsole mainboard it has these ports allocated:
| Port | Destination |
|---|---|
| 1 | Internal — keyboard GD32 USB-HID |
| 2 | Internal — wired to the USB-A jack on the side of the case |
| 3 | Internal — Mini PCIe slot’s USB pair |
| 4 | Reserved (test pads only) |
The hub is fed SYS_5V and SYS_3V3 (logic). It uses an external 24 MHz crystal (X501) for its USB clock domain. Configuration straps (PSELF, OVCUR1#/2#, PWREN1#/2#) are tied to SYS_3V3 or GND per the GL850G datasheet’s “self-powered hub, 4 downstream ports, individual port power control” mode.
9.2 USB-A power switch
U502: SY6280 (V3.14) or TPS2553 (V3.14_V5)1112 is the USB-A Vbus power switch. It accepts the GL850G’s “Power Enable” signal (active-low) and connects SYS_5V to the USB-A jack’s Vbus when asserted. It also has a current-limit (1.5 A typical for SY6280, programmable via RILIM for TPS2553) and over-current flag back to the hub. If you plug a high-draw device into the USB-A and exceed the limit, the switch trips, the hub gets the OC flag, and Linux logs a port disabled event.
9.3 USB-C — the charge-and-data path
The USB-C jack on the mainboard handles two things:
- Charge: 5 V at up to 2 A from a wall wart, routed through CC1/CC2 termination resistors into the AXP228’s
IPSOUTcharger input. - Data: D+/D− from the USB-C jack are routed to a port on the CM directly (not through the GL850G hub). This is the path the CM4’s USB-MSD recovery uses when
nRPIBOOTis asserted (Vol 4 §4.4).
The mainboard does not implement USB-PD negotiation. The 5.1 kΩ CC pull-down resistors signal “device, default 5 V 3 A capability.” A USB-PD source will offer 5 V; higher voltages won’t be requested. This is the principal limitation that the V5 revision addresses partially (the TPS61178 boost can supply CM5’s higher peak draw under battery alone, but the input is still capped by what a non-PD wall wart provides).
10. HDMI Path
HDMI0 from the CM connector is a 4-pair TMDS bus (3 × differential data + 1 × differential clock) plus single-ended HDMI_CEC, HDMI_HPD_N, HDMI_SDA, HDMI_SCL. All eight signals are routed through U301: ESD538413 for ESD protection — a 4-line common-mode-choke + TVS array specifically designed for HDMI/DisplayPort/USB-3 high-speed differential pairs. The CMC component on the same package suppresses common-mode noise on the TMDS pairs while pass-through differential.
HDMI_HPD_N_1V8 is level-shifted from the CM’s 1.8 V signal to a 5 V-tolerant logic level via a small BSS138 N-MOS / 10 K pull-up topology (the canonical “level shifter” — Vladimir Mavrodiev’s circuit). The HDMI sink (TV) sees a normal 5 V hot-plug detect signal; the CM sees a 1.8 V logic level.
The micro-HDMI jack (J501) is a standard female micro-HDMI Type D connector with internal ESD-509 array on the data lines and shielded backshell.
11. The 40-pin GPIO Header
The 40-pin header on the back of the case exposes GPIO 0-27 of the CM, with the canonical Pi pinout. The mainboard does not level-shift or buffer these signals — they’re direct 3.3 V CMOS from the CM. This means:
- You can plug in any standard Raspberry Pi HAT and it will work physically.
- You can plug in 5 V-logic devices and you will damage the CM.
- The total current draw across all 3.3 V pins is summed and limited to ~50 mA by the CM’s internal 3.3 V regulator.
The schematic shows ID_SD and ID_SC (the HAT EEPROM pins, GPIO 0/1) connected directly to the connector — no termination, no protection. If you spill 5 V to those pins you brick the CM’s HAT-detection. Treat as DNC (do-not-connect) unless you know HAT discipline. (Vol 12 §2.1 has the pinout cheat; this volume gives you the why.)
The 5 V pins on the header (pins 2 and 4) are tied to SYS_5V directly — so HATs that draw 5 V are sharing the same rail as the audio amps and USB hub. A high-draw HAT (a fan board, a high-current servo controller) will audibly affect the speakers if you don’t add additional decoupling.
12. The Mini PCIe Slot
The 52-pin Mini PCIe slot14 is the differentiator that elevates the uConsole from “Pi 4 in a case” to “field-deployment cyberdeck.” It exposes:
| Pin | Signal | Mainboard handling |
|---|---|---|
| 11/13 | REFCLK ± | 100 MHz differential clock from CM |
| 23/25 | PERn / PERp | PCIe receive lane (CM TX → card RX) |
| 31/33 | PETn / PETp | PCIe transmit lane (card TX → CM RX) |
| 36/38 | USB D− / D+ | USB 2.0 alternate function (routed to GL850G port 3) |
| 8/10 | UIM_PWR / UIM_RST | SIM-card power / reset (LTE modem cards) |
| 2/24/41/52 | +3.3V Vcc | From SYS_3V3 |
| 9/14/18/26/39 | GND | Multiple grounds |
The slot is wired so that either the PCIe pair or the USB pair is in use, depending on what the card asserts via its CC strap. RTL-SDR Mini, USB-only LTE modems, and most cellular hardware go through the USB path. NVMe SSDs (via Mini-PCIe-to-NVMe adapter) and dedicated PCIe SDR cards take the PCIe path.
CM4’s PCIe is a single ×1 lane at Gen 2 (5 GT/s); CM5 ups this to Gen 2 as well (still ×1) but with better signal integrity. Volume 7 §7.3 has the full electrical pinout and the compatibility-card matrix.
13. The CM Adapter Card
Between the mainboard’s two DF40C sockets and the actual Compute Module sits an adapter card — a small PCB that takes the CM’s connector and breaks it out to whatever the mainboard expects. The adapter is what makes the CM4 / CM5 / Radxa swap-able. The schematic for the stock CM4 adapter is clockwork_Adapter_CM4_Schematic.pdf.
13.1 What the adapter does
For the CM4 adapter specifically:
- Power input: takes
CM_VBAT(≈4.2 V from the AXP228 DCDC2) and boosts it to a regulated 5 V on the CM-side via U1: ETA109615, with a 2.2 µH / 10 A inductor (L1) and a 22 µF / 10 V output cap. That 5 V powers the CM4’s on-module SMPS. - Signal pass-through: routes DSI0/1, HDMI0/1, USB host, GPIO group A & B, CAM0/1, SD pins, and control signals (
RUN,nEXTRST,GLOBAL_EN, etc.) one-to-one between the mainboard’s two DF40C sockets and the CM4’s mezzanine pinout. - Status indication: the small green LED (
PI_LED_nPWRfrom the CM) is exposed on the adapter for diagnostic visibility.
13.2 Why adapters matter for this series
Vol 3 covers compute-module compatibility in depth; the short story is that swapping a CM5 in place of a CM4 requires either a different adapter (HackerGadgets sells one) or a re-routed mainboard rev (V3.14_V5). The adapter abstracts the CM’s specific pin assignments for things like additional PCIe lanes, dedicated I²S audio (CM5 has it; CM4 doesn’t), and the small power-rail differences.
14. The PMIC Latch Quirk and POWER_OFF_ON_HALT
The most-discussed gotcha on the uConsole community forums is the “dim green LED, won’t reboot” state — the device looks half-on, the power button is unresponsive, and a normal reboot doesn’t help. The root cause is in the AXP228 + CM4 interaction:
- On a normal
sudo shutdown -h now, Linux halts and the kernel assertsnEXTRSTlow. The CM stops executing. - But by default, the AXP228 doesn’t drop its rails. The PMIC stays powered up, the rails stay live. The CM is reset but the system’s downstream loads (LCD backlight, GL850G hub, audio amps) are still drawing — at micro-amp levels but accumulating fast on a small battery.
- The “PWROK” handshake the AXP228 expects is broken because the CM is in reset, not in a clean low-power state. The PMIC’s internal state machine sits in a “limbo” that prevents a fresh power-on from succeeding.
The fix is the POWER_OFF_ON_HALT=1 EEPROM setting on the CM:
sudo rpi-eeprom-config --edit
# add this line:
POWER_OFF_ON_HALT=1This tells the CM bootloader to actively drive RUN low (and signal the PMIC via I²C) on a clean shutdown, so the AXP228 does drop its rails. Next power-on starts clean.
If you ever do hit the latch state in the field: pop the back, pull the 18650s for 10 seconds, reseat them. That cold-reset clears the PMIC’s internal state. Don’t rely on the long-press button — that also needs the PMIC to respond to PWRON, which is part of what’s stuck.
This is documented in the legacy uConsole single-doc deep dive16 and in the community Bookworm/Trixie image notes; the Clockwork forum has dozens of threads about it.
15. The 18650 Battery Sub-system
The mainboard accepts two 18650 cells in parallel. The schematic shows:
- Each cell holder’s positive terminal goes through a small fuse (
F1,F2— typically 5 A polyfuse) to the mergedVBATnet. - Each cell holder’s negative terminal goes through a separate sense resistor (
R1,R2 — 0R01 1%) to ground for per-cell coulomb counting (the AXP228 supports independent cell measurement). - A reverse-polarity protection MOSFET (
Q1) sits betweenVBATandIPSOUT. Polarity-reversed cell insertion is detected (the body diode conducts the wrong way), and the MOSFET stays off — the device just refuses to power on rather than fragging the rest of the circuit.
The cells are merged into a single equivalent ~3.0–4.2 V, ~6 Ah pack. The AXP228 charges them as a single unit (Coulomb-count adjusted for the parallel capacity). At full charge (4.2 V × 6 Ah) the pack stores ~25 Wh — translated through 80 % conversion efficiency, that’s ~20 Wh available to the system. At a typical CM4 + LCD + radio active draw of 5–6 W, that’s the ~3.5 hour real-world figure quoted in Vol 1.
Two cells in parallel rather than series is a deliberate design choice: it keeps the system rail at single-cell levels (so the PMIC’s switching topology is simpler), it lets you mix-and-match cell capacities without mismatch issues at first-order (parallel cells equalise themselves), and it makes the user-replaceable cell story easier (no series-pack BMS to worry about).
16. Clocks, Crystals, Resets
The mainboard has no SoC-level crystal — that’s all on the CM module. The mainboard’s crystals are subsystem-local:
| Reference | Frequency | Subsystem |
|---|---|---|
X501 | 24 MHz | GL850G USB hub clock |
X1 (kbd) | 8 MHz | GD32 keyboard MCU HSE |
X2 (kbd) | 32.768 kHz | GD32 keyboard MCU LSE / RTC |
The AXP228 has its own internal oscillator for I²C / fuel-gauge timing, no external crystal needed.
Reset distribution:
nEXTRST(mainboard) → CM (forces CM reset)RUN(mainboard) → CM enable (gated by AXP228PWROK)- AXP228 internal reset on long-press of
PWRON - GD32 reset on
NRST(R1 pull-up + C5 100 nF cap to ground = standard ST RC reset network)
17. Mainboard V3.14 → V3.14_V5: What Changed
A pin-for-pin and net-for-net comparison of the two schematics shows only two meaningful component changes:
| Reference | V3.14 (stock) | V3.14_V5 (CM5-ready) | Why |
|---|---|---|---|
| U502 | SY6280 | TPS2553 | Better thermal envelope; programmable current limit |
| (5V boost) | SY7215 LDO | TPS61178 boost | Higher peak current, better efficiency for CM5 loads |
That’s it. PCB layout differences are minor: the V5 has a slightly larger inductor footprint (for the TPS61178’s 5.5 A inductor) and a wider trace from the boost output to SYS_5V. Net topology, pin assignments, signal routing, and connector positions are identical.
If you have a V3.14 mainboard and want CM5 support, you don’t need to swap to V5 — you need either (a) a CM5-aware CM adapter from HackerGadgets that has a stronger boost stage on its own side, or (b) a willingness to limit the CM5 to its lower power-state envelope (governor=powersave, no NVMe, no mPCIe high-power devices). Option (a) is the practical path; option (b) works for casual use.
18. BOM and Sourcing
A reduced BOM for the mainboard’s “principal components” (the things that, if they fail, you have to replace; not capacitors and resistors). Refer to the schematic for full passives.
| Reference | Part | Function | Source / Distributor |
|---|---|---|---|
| U101 | AXP228 | System PMIC | LCSC C71017 / X-Powers |
| U501 | GL850G | USB 2.0 hub controller | Mouser 869-GL850G / Genesys Logic |
| U502 (V3.14) | SY6280 | USB-A power switch | LCSC C107383 / Silergy |
| U502 (V5) | TPS2553 | USB-A power switch | TI distributor / Mouser |
| U301 | ESD5384 | HDMI ESD/CMC array | Diodes / Mouser |
| U302 | (Backlight) | LCD backlight boost driver | Custom / generic boost IC |
| U401-U404 | OCP8178 | Class-D speaker amps | LCSC C476929 / OCP |
| (Audio sw) | AS4729 | Audio analog switch | LCSC / Astar |
| (CM4 ada) | ETA1096 | Battery → 5V boost on CM adapter | LCSC / Etasolar |
| (Kbd MCU) | GD32F103Rx | Keyboard MCU | LCSC C82475 / GigaDevice |
| (Kbd LDO) | LM1117S-3.3 | Keyboard 3.3V LDO | LCSC C7843 / TI / Onsemi |
| (CM conn) | DF40C-100DS-0.4V | CM mezzanine connector (×2) | Hirose / Digi-Key 798-DF40C100DS04V |
| LCD | JD9365DA-H3 | LCD driver IC | Fitipower (panel sub-assembly only) |
LCSC part numbers above are the closest verifiable matches; some are the manufacturer’s preferred LCSC rather than the exact SKU on the Clockwork BOM. Always double-check the LCSC datasheet against the schematic before ordering replacements.
19. Maintenance & Field Repair
For tjscientist (and any reader doing in-the-field work):
- Mainboard fuses (
F1,F2polyfuses on the battery rails) self-reset after a brief over-current. If they’re cycling, you have a short-to-ground somewhere downstream. Pull all add-on cards (mPCIe, GPIO HAT, USB-A devices) and try again. - The AXP228 is socketed to the mainboard via a small QFN footprint. Hot-air rework is feasible if you have a station; the IC itself is ~$2 from LCSC.
- The DF40C connectors are spec’d for 50 mating cycles. After ~30 cycles they become slightly less reliable. If you’re prototyping on the bench and swapping CMs frequently, plan to reflow-replace the sockets eventually. The mainboard PCB is robust enough to survive several connector replacements.
- The keyboard ribbon cable is the most mechanically-stressed connection in the device. If keys go unresponsive, suspect the cable before suspecting the GD32.
- The LCD FPC connector is fragile; the panel is rated for 30 mating cycles. Don’t disconnect it casually.
20. Resources
| Topic | URL |
|---|---|
| Mainboard V3.14 schematic | https://github.com/clockworkpi/uConsole/raw/master/clockwork_Mainboard_V3.14_Schematic.pdf |
| Mainboard V3.14_V5 schematic | https://github.com/clockworkpi/uConsole/raw/master/clockwork_Mainboard_V3.14_V5_Schematic.pdf |
| CM4 adapter schematic | https://github.com/clockworkpi/uConsole/raw/master/clockwork_Adapter_CM4_Schematic.pdf |
| Keyboard MCU schematic | https://github.com/clockworkpi/uConsole/raw/master/keyboard_220816.pdf |
| Assembly guidelines (PDF) | https://github.com/clockworkpi/uConsole/raw/master/Clockwork_uConsole_Assembly_Guidelines.pdf |
| JD9365DA-H3 datasheet | https://github.com/clockworkpi/uConsole/raw/master/JD9365DA-H3_DS_V0.01_20200819.pdf |
| AXP228 datasheet (X-Powers) | http://www.x-powers.com/ |
| GL850G datasheet (Genesys Logic) | https://www.genesyslogic.com/ |
| Raspberry Pi CM4 datasheet | https://datasheets.raspberrypi.com/cm4/cm4-datasheet.pdf |
| Raspberry Pi CM5 datasheet | https://datasheets.raspberrypi.com/cm5/cm5-datasheet.pdf |
| Hirose DF40 connector datasheet | https://www.hirose.com/ |
| Clockwork forum (uConsole subforum) | https://forum.clockworkpi.com/c/uconsole/ |
21. Index
A — Adapter (CM) — §13. ALDO — §3.3, §4. Audio path — §7. AS4729 — §7.3. AXP228 — §3.
B — Backlight — §6.2. Battery — §3.4, §15. BCM2711 — §7.1. Boost converter — §3.2, §13.1, §17. BSS138 — §10.
C — CM connector — §5. CM4 adapter — §13. Codec — §7.1. Crystals — §16. Current limit — §9.2.
D — DCDC — §3.2, §4. Decoupling — §3.2 footnote. DF40C — §5, §19. Display path — §6. DSI — §6.1.
E — eMMC — Vol 4 (cross-ref). ESD5384 — §10. ETA1096 — §13.1.
F — Fuel-gauge — §3.4. Functional block — §2. Fuses — §15, §19.
G — GD32F103 — §8, §16. GL850G — §9.1. GPIO header — §11.
H — HAT — §11. HDMI — §10. Headphone jack — §7.3, §7.4. Hirose — §5.
I — I²C (PMU bus) — §3, §3.5. IPS — §4. IRQ — §3.5. JD9365 — §6.
K — Keyboard — §8. Keyboard backlight — §8.1, §11.3 (Vol 12 cross-ref).
L — Latch (PMIC) — §14. LCD — §6. LDO — §3.3. LM1117 — §8. Low-power-state — §17.
M — Microphone — §7.4. Mini PCIe — §12. Mainboard rev — §1, §17. Modulation (PWM audio) — §7.1.
N — Net names — §3.2, §4, §5.2. nEXTRST — §5.2, §16.
O — OCP8178 — §7.2. Open-collector — N/A.
P — PCIe — §12. PMIC — §3, §14. POWER_OFF_ON_HALT — §14. Power tree — §4. PWRON — §3.5.
Q — QFN — §19.
R — Reset — §16. Revision (V3.14 vs V5) — §17. RUN — §5.2.
S — Schematic — §1 (footnote 1). SD card — §5.1. Slot — §12. Speakers — §7. SY6280 — §9.2.
T — Thermal — §7.2, §19. TMDS — §10. TPS2553 — §9.2, §17. TPS61178 — §17.
U — USB hub — §9.1. USB-A — §9.2. USB-C — §9.3.
V — VBAT — §15. Voltage rails — §4.
W — WIFI_VBAT, WIFI_VDD — §3.3, §4.
X — X-Powers — §3.
Y, Z — None.
Footnotes
-
https://github.com/clockworkpi/uConsole— the canonical Clockwork repository. Schematics are at the repo root:clockwork_Mainboard_V3.14_Schematic.pdf(stock CM4 mainboard),clockwork_Mainboard_V3.14_V5_Schematic.pdf(CM5-friendly revision),clockwork_Adapter_CM4_Schematic.pdf(CM mezzanine-to-mainboard adapter),keyboard_220816.pdf(keyboard MCU), andClockwork_uConsole_Assembly_Guidelines.pdf. All five files are mirrored into02-inputs/schematics/for offline reference. ↩ -
AXP228 datasheet: typical X-Powers product page at
http://www.x-powers.com/. The chip is the descendant of the AXP223 used in the GameShell and DevTerm; the PicoCalc Volume 2 readers will recognise the family (PicoCalc uses an AXP2101 — same vendor, different product line, similar architecture). ↩ -
Clockwork_uConsole_Assembly_Guidelines.pdf— “Use ONLY 5V-2A USB-C charger.” The 2 A figure is the input limit; the AXP228’s actual charge current to the cells is set in firmware via I²C registers and is well under that. ↩ -
Hirose DF40C-100DS-0.4V — datasheet:
https://www.hirose.com/. 0.4 mm pitch, 1.5 mm height, 100 contacts each, 0.7 A current rating per contact, ENIG plating. ↩ -
Raspberry Pi CM4 datasheet, §7 “Connector pinout” —
https://datasheets.raspberrypi.com/cm4/cm4-datasheet.pdf. The CM5 datasheet (cm5-datasheet.pdf) maintains pinout compatibility with a handful of redefined pins for additional PCIe lanes; §3.3 of this volume’s compute-module-companion volume (Vol 3) details the differences. ↩ -
JD9365DA-H3_DS_V0.01_20200819.pdf— JD9365DA-H3 datasheet (Fitipower, 1280-RGB×800 capable; configured for 1280×720 in the uConsole); mirrored at02-inputs/datasheets/JD9365DA-H3_DS_V0.01_20200819.pdf. The user guideJD9365DA-H3_User_Guide_Preliminary_V0.00_20200827.pdfcovers the panel command set. ↩ -
OCP8178 — Originally Costed Power, datasheet at
http://www.ocp.com.tw/. Class-D mono speaker amp, 2.5–5.5 V supply, up to 3 W into 4 Ω at 5 V. Common across hobbyist handheld designs; its quirky thermal-shutdown threshold (~120 °C) is why the case has a small thermal pad routed near U401-U404. ↩ -
GD32F103Rx — GigaDevice Semiconductor, datasheet at
https://www.gigadevice.com/. Cortex-M3 at 108 MHz, 64–128 KB flash, 20 KB SRAM, 64-pin LQFP. Drop-in software- and pin-compatible with STMicro’s STM32F103R8T6/RBT6. Picked here for cost and supply (GigaDevice has been more available than ST during silicon shortages). ↩ -
LM1117S-3.3 — Texas Instruments / Onsemi; SOT-223 package; 800 mA continuous, dropout typical 1.2 V. Adequate for the GD32 + a few mA of pull-ups. ↩
-
GL850G — Genesys Logic, datasheet at
https://www.genesyslogic.com/. 4-port USB 2.0 hub, single-TT, 28-pin SSOP. ~7 mA quiescent, ~25 mA active. ↩ -
SY6280 — Silergy Semiconductor, datasheet at
https://www.silergy.com/. 1.5 A current-limited high-side P-MOS switch, 12 mΩ on-resistance, integrated thermal shutdown. ↩ -
TPS2553 — Texas Instruments, datasheet at
https://www.ti.com/product/TPS2553. Programmable current limit (75 mA – 2.5 A viaRILIM), 100 mΩ on-resistance, fast-trip OC fault, integrated reverse-current blocking. Pin-compatible upgrade from SY6280 for V5. ↩ -
ESD5384 — Diodes Incorporated, datasheet at
https://www.diodes.com/. 4-line common-mode-choke + ESD TVS array, 6 V working voltage, sub-1 pF capacitance per line, rated for HDMI 2.0 (4K @ 60 Hz). The choice for hobby-grade Pi-shaped boards. ↩ -
PCI-SIG Mini PCIe Card Specification — public via PCI-SIG. The 52-pin connector with the standard 0.8 mm pitch is what every hobbyist mPCIe card uses. ↩
-
ETA1096 — Etasolar / Etaron Semiconductor, datasheet at
https://etasolar.com/. Synchronous boost converter, 2.7–5.5 V input, programmable output via feedback resistor (220 kΩ in this design = ≈5.0 V output), up to 5 A output current, 1.5 MHz switching, integrated dual MOSFETs. ↩ -
02-inputs/uconsole-full-loadout-manual.md.docx— the prior-session deep-dive reference, §5.4 “The PMIC Latch Problem.” Useful as a community-knowledge confirmation; this volume’s treatment derives the why from the schematic. ↩